A 12-bit CMOS Ratio-Independent Algorithmic Analog-to-Digital Converter

This paper proposes a 1.5 V 12-b CMOS ratio-independent algorithmic analog-to-digital converter (ADC) based on a capacitor-mismatch insensitive technique. A novel switched-capacitor multiplying digital-to-analog converter (MDAC) with an accurate gain of two is proposed for an algorithmic ADC. The proposed MDAC architecture requires only one opamp in four phases to generate the next residue output voltage. It significantly suppresses the gain error caused by a capacitor mismatch. Furthermore, bootstrapped switches are used to achieve rail-to-rail signal swing at low-voltage power supply. This ADC design achieves a DNL and INL of 0.36 LSB and 0.45 LSB, respectively, while the SNDR is 61.8 dB and SFDR is 69.5 dB at an input frequency of 400 kHz. Operating at a 5 MS/s sampling rate using a single 1.5 V power supply, the power consumption is 4.8 mW in a TSMC 0.18 μm CMOS 1P6M process.